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MRF49XA
RESET ........................................................................ 12
RFN............................................................................. 12
RFP ............................................................................. 12
RFXTL/EXTREF ......................................................... 12
RSSIO......................................................................... 12
SCK............................................................................. 11
SDI .............................................................................. 11
SDO ............................................................................ 11
V DD .............................................................................. 12
V SS .............................................................................. 12
Power and Low Noise Amplifiers ........................................ 47
Power Management ............................................................ 61
Power-Saving Modes
Low Battery Voltage Detector ..................................... 16
Low Duty Cycle Mode ................................................. 16
Wake-up Timer ........................................................... 16
Programmable Synchronous Byte ...................................... 59
R
Reader Response ............................................................. 100
Receive FIFO ...................................................................... 17
Receive Signal Strength Indicator (RSSI) ........................... 15
Received Signal Strength Indicator (RSSI) ......................... 59
Recommended Operating Conditions ................................. 80
Recovery Clock Output ....................................................... 11
Register Map....................................................................... 42
Registers
AFCCREG (Automatic Frequency Control Configuration)
22
BBFCREG (Baseband Filter Configuration)................ 29
BCSREG (Battery Threshold Detect and Clock Output
Value Set) ........................................................... 40
CFSREG (Center Frequency Value Set) .................... 26
DCSREG (Duty Cycle Value Set) ............................... 39
DRSREG (Data Rate Value Set) ................................ 35
FIFORSTREG (FIFO and Reset Mode Configuration) 32
GENCREG (General Configuration) ........................... 21
PLLCREG (PLL Configuration) ................................... 41
PMCREG (Power Management Configuration) .......... 36
RXCREG (Receive Control)........................................ 27
RXFIFOREG (Receiver FIFO Read)........................... 31
STSREG (STATUS Read) .......................................... 19
SYNBREG (Synchronous Byte Configuration) ........... 34
TXBREG (Transmit Byte)............................................ 25
TXCREG (Transmit Configuration) ............................. 23
WTSREG (Wake-up Timer Value Set)........................ 38
Reset
Power Glitch Reset ..................................................... 44
Power-on Reset .......................................................... 43
RESET Pin.................................................................. 45
Software Reset ........................................................... 45
Reset Mode Selection ......................................................... 33
RESET Pin .......................................................................... 13
Revision History .................................................................. 95
RF Crystal ........................................................................... 12
RF Transmitter Matching..................................................... 74
RF/Analog Features .............................................................. 3
RX FIFO Buffered Data Read ............................................. 70
RX-TX Frequency Alignment Method ................................. 72
S
Schematics
MRF49XA ................................................................... 76
Serial Peripheral Interface (SPI) ......................................... 17
Sleep, Wake-up and Battery Operations............................. 65
SPI
Timing Specification.................................................... 84
Synchronous Character Selection ...................................... 33
T
Timing Diagrams
FIFO Read with FINT Polling...................................... 71
FSK Modulated Deviation (Max. TX to RX Offset)...... 57
Low-Power Duty Cycle Mode Sequence .................... 64
Multiple Byte Write with Transmit Register ................. 69
Power-on Reset Example ........................................... 43
Receiver FIFO Read................................................... 70
Sensitive Reset Disabled............................................ 45
Sensitive Reset Enabled............................................. 44
SPI .............................................................................. 84
STSREG Read Sequence .......................................... 93
TX Register Usage ..................................................... 69
Transmit Register ............................................................... 16
TX Register Buffered Data Transmission ........................... 66
Typical Applications .............................................................. 3
V
V DD Line Filtering................................................................ 46
W
Wake-up Timer ................................................................... 16
WWW Address ................................................................... 99
WWW, On-Line Support ....................................................... 5
DS70590C-page 98
Preliminary
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